FIG. 67 shows a conventional drive circuit. In FIG. 67, reference numeral 1 denotes a drive circuit power supply such as a battery, 2 a battery voltage terminal VB, 3 a clock input terminal CLK, 4 a grounding terminal GND, 5 a top arm control signal input terminal IT, 6 a bottom arm control input terminal IB, 7 a voltage boosting power supply circuit, 8 a pre-drive circuit for driving a totem-pole type output stage of the next stage, 9 a top arm driver for driving an NMOS transistor 11 (hereafter referred to as top arm transistor, or simply top arm) included in the totem-pole type output stage in the pre-drive circuit 8, 10 a bottom arm driver for driving an NMOS transistor 12 (hereafter referred to as bottom arm transistor, or simply bottom arm) included in the totem-pole type output stage in the pre-drive circuit 8, and 13 an output terminal connected to a load.
A case will now be explained in which the drive circuit power supply 1 connected to the VB terminal 2 and the GND terminal 4 is a battery power supply that drives the load connected to the terminal 13 based on the operation of pulse width modulation (PWM). As for operation of the output stage, the direction of a current that flows through the load connected to the output terminal 13 can be controlled by ejecting (sourcing, or pushing) a current to the output when the top arm 11 is on and the bottom arm 12 is off, and absorbing (sinking or pulling) the current when the top arm 11 is off and the bottom arm 12 is on.
In the instance of a current source in which the top arm 11 is on and the bottom arm 12 is off, the voltage of the output terminal 13 rises up to the power supply voltage (battery voltage) VB. At this time, therefore, VB+Vgs becomes necessary as a gate high voltage of the top arm 11, where Vgs is a gate-source voltage required to drive the NMOS transistor 11. In other words, a power supply voltage higher than the battery voltage VB becomes necessary. Therefore, the voltage boosting power supply circuit 7 is provided.
A charge pump circuit that requires a clock input signal or a step-up converter is used for the voltage boosting power supply circuit 7. A voltage boosted therein is used as a power supply of the top arm driver 9 in the pre-drive circuit 8. An output voltage of the drive circuit power supply 1 is typically supplied from the VB terminal 2 as a power supply of the bottom arm driver 10.
A more concrete circuit example of FIG. 67 is shown in FIG. 68. As an example of the voltage boosting power supply circuit 7, a charge pump circuit that double-boosts a voltage based on the power supply voltage VB as a reference voltage is shown. Reference numerals 40 and 41 denote rectifier diodes, 43 a pile-up capacitor for boosting, 45 a decoupling capacitor for a boosted output voltage, 46 a PMOS transistor, and 47 an NMOS transistor. These components form an inverter for charging the capacitor 43.
The pre-drive circuit 8 includes a top control circuit 51 and a bottom arm controller 52. The top arm controller 51 receives a top arm control signal from the IT input terminal 5, and activates a top arm drive inverter formed of a PMOS transistor 57 and an NMOS transistor 58. The bottom arm controller 52 receives a bottom arm control signal from the IB input terminal 6, and activates a bottom arm drive inverter formed of a PMOS transistor 59 and an NMOS transistor 60. Resistors 61 and 62 are gate resistors for adjusting switching speeds of the top arm 11 and the bottom arm 12, respectively.
Supposing that the power supply voltage VB is 20 V, at least 20 V is required as a drain-source withstanding voltage of the output stage transistors 11 and 12. Since the power supply of the bottom arm driver is VB, at least 20 V becomes necessary as the withstanding voltage of the transistors 59 and 60 and the bottom arm controller 52 as well. As for the top arm driver, the voltage boosting power supply circuit 7 outputting an output of the charge pump circuit, which boosts the voltage to twice, is used as a power supply. Neglecting the voltage loss in circuit elements, the output voltage of the charge pump becomes 40V. Therefore, at least 40 V becomes necessary as a withstanding voltage of the top arm controller 51, and the transistors 57 and 58.
Typically, in MOS transistors each having a high withstanding voltage, the gate-source withstanding voltage is small as compared with the drain-source withstanding voltage. In order to prevent over voltage gate-source breakdown of the transistors each having a withstanding voltage of 20 V or 40 V, Zener diodes 53 to 56, 63 and 64 become necessary. For the same reason, gate-source protection Zener diodes 505 and 506 become necessary also for the transistors 46 and 47, which form an inverter in the voltage boosting power supply circuit 7.
The conventional drive circuit shown in FIG. 67 and FIG. 68 has problems as mentioned below.
First, when a power supply such as a battery in which a power supply voltage varies greatly (“large in power supply voltage variation”) is used and the power supply voltage has fallen, the output current drive capability of the bottom arm cannot be exhibited sufficiently. For example, if a battery of 12 V is used as a power supply, the voltage becomes approximately 16 V when the battery is fully charged and the voltage becomes approximately 6 V when the battery voltage has fallen. Such a variation of the operation power supply voltage must be considered. For example, when the battery voltage has fallen, the gate input high voltage of the bottom arm becomes 6 V. A voltage in the range of approximately 8 to 10 V is typically needed as the gate-source voltage, although it depends upon the output current and the characteristic of the NMOS transistor 12 as well. When the battery voltage is 6 V, therefore, on-resistance of the bottom arm transistor becomes lower and a required output sink current cannot be obtained.
A second problem is as follows, when a power supply having a large power supply voltage variation, such as a battery power supply, is used, it becomes necessary to use a circuit designed with due regard to a maximum power supply voltage and a larger voltage than needed is applied to the output gate sometimes. For example, the gate-source voltage required for driving each of the output stage transistors is in the range of approximately 8 to 10 V, although it depends upon the output current and the NMOS device characteristic as well. If a power supply of, for example, VB=24 V is used in the circuit of FIG. 68, the power supply voltage of the top arm driver 9 and the power supply voltage of the bottom arm driver 10 become 48 V and 24 V, respectively, neglecting the voltage loss within the charge pump circuit. The power supply voltages thus become very large as compared with the necessary drive voltage in the range of 8 to 10 V of the output stage transistors.
Especially, a top arm driver power supply voltage of 24 V+10 V=34 V is sufficient considering the numerical values. As a matter of fact, however, the top arm driver power supply voltage becomes an unnecessarily excessive voltage of 48 V.
If the power supply voltage becomes excessively large, noise generated at the time of circuit operation also increases. If the power supply voltage is made larger than needed, then the influence of the power supply noise and GND noise on circuit operation or the influence of radiation noise on the external electric circuit readily occurs, which is undesirable. Since withstanding voltage of the voltage boosting power supply circuit 7 and the pre-drive circuit 8 depend on the power supply voltage VB, elements each having a withstanding voltage corresponding to the maximum voltage of VB must be used as most elements forming the circuit. In addition, it also becomes necessary to add protection circuits such as the gate protection circuits.
These unfavorably result in an increased manufacturing cost, because they expand the layout pattern areas of individual elements in integrated circuits, and increase unit prices of element components in electric circuits formed of discrete components.
Thirdly, it also poses a problem that an influence of a variation of circuit characteristics caused by a variation of the power supply voltage appears in the output stage operation when a power supply having a large power supply voltage variation is used.
To be concrete, the operation delay of the top arm driver 9 or the bottom arm driver 10 is changed by the power supply voltage variation. Due to a change of on-resistance of the transistors 57 to 60, which drive the top arm 11 and the bottom arm 12 serving as output transistors, the switching speed of the output transistors varies. In order to prevent the characteristic variation, further a circuit is required to be added, resulting in an increased circuit scale and an increased manufacturing cost.